A. Technical Field
The present invention relates generally to electronic design automation (“EDA”) tools, and more particularly, to the verification of an extracted timing model generated for a block, macro or core.
B. Background of the Invention
The importance and rapid growth of electronics technology is well known. Integrated electrical systems are continually being reduced in size while continually increasing in design complexity. These advancements have led to rising clock frequencies and shrinking process geometries, increasing the emphasis on signal integrity effects such as IR drops, crosstalk delay and other noise features.
The design of a System-On-Clip (SOC) involves integration of several blocks differing in functionality. In order to minimize the time in designing such complex systems, design reuse has drastically increased in the development of electrical systems. For example, a System-On-Chip (“SOC”) may comprise a large number of macros or cores that are designed into a system by multiple engineers or engineering teams. Oftentimes, the design process of a SOC requires that timing components and characteristics of the macros or cores be provided to the various engineers to ensure compatibility between the macros within the SOC. These macros and cores generally include Intellectual Property blocks or cells (“cells”) that allow the design to be reused across multiple systems, which further necessitates the need for modeling the timing characteristics of block, macro or core.
Timing characteristics of a cell may be described in an extracted timing model (“ETM”). An ETM describes timing components of the inputs and outputs of the cell. Accordingly, a designer can use an ETM to ensure that other cells within a macro, core and SOC are able to properly interface and effectively communicate within the system. ETMs may be difficult to generate depending on the complexity of the cell that is being modeled. Oftentimes, ETM files must be manually built in order to generate an ETM for a particular cell.
Once this ETM file is generated, it may be used internally within a company to design a system or provided to a customer to allow integration of a cell within a customer's system. One example of an ETM file is the library (“.lib”) file that corresponds to an original netlist for the cell. As shown in FIG. 1, a user 102 manually generates the .lib file 101 that describes timing characteristics of a cell. This .lib file may be provided to a vendor or customer 103 to allow proper integration of a corresponding cell within a system.
The .lib file contains information that describes timing arcs between input and output pins of a design cell. These timing arcs may contain timing tables which describe timing characteristics between the input and output pins. In particular, the timing tables define timing values as a function of input transition time and output loading. The .lib file may also contain min_periods and area_number attributes.
The .lib files containing timing arcs and tables are used for modeling the timing of input and output pins without involving actual internal nets implementation details. For instance, if a designer needs to integrate a number of different cells in the core, he/she makes use of these .lib files to gain the timing information of the core. Sometimes customers use the timing models depending upon the design stages.
PrimeTime™ is a gate-level static timing analysis tool that is optimized to analyze millions of gates in a short time. Manual generation of a .lib file to model the netlist for which an ETM file is generated may be required when using a delay calculator other than the PrimeTime™ calculator. In such an instance, an engineer is required to manually code the .lib file, which may be complicated and require a large amount of time. An engineer may want to avoid using the PrimeTime™ delay calculator because of the associated cost aspects or its inability to address other signal characteristics such as cross talk and noise.
The PrimeTime™ graphical user interface and command line may be complicated or otherwise difficult for an inexperienced engineer to properly generate an ETM. This interface and manual process of building a .lib file may be complicated, error prone and time consuming. PrimeTime™ also fails to provide certain boundaries or constraints during the generation of an ETM. For example, a user may incorrectly provide a signal frequency or period outside of an appropriate range. Other user input may fall outside of a particular operable boundary resulting in an inappropriate ETM.
The creation of a timing model may involve several iterations. Once a model is created, it is oftentimes essential to validate it relative to different parameters. For example, a validation process may include manually comparing the timing values of the model created to the gate-level netlist.
Effective validation of the model created enables reduction in time to market by overcoming the need of re-verification. The accuracy of the timing model is thus essential in core-based design. In addition, as the number of iterations within the generation of the timing model is reduced, the design time of the electrical system is reduced.
Presently, a verification process is performed manually wherein all the necessary steps required to create and validate an extracted timing model file are checked one-by-one by an individual. This manual process is oftentimes error prone and time consuming. Furthermore, the complexity of the validation process may increase if various steps need to be followed in right order to achieve the aimed model.